1. Field of Invention
The present invention relates to a pixel circuitry for a display apparatus, and more particular, to a pixel circuitry that increases a voltage range of a pixel signal passing through a scan switch to a pixel electrode, and/or increases a capacitance of a storage element for storing the pixel signal under low operation frequency.
2. Description of the Related Art
A display panel of a liquid crystal display (LCD) is composed of a pixel array which includes a plurality of pixel circuitries. FIG. 1A is a circuit diagram of a conventional pixel circuitry. Referring to FIG. 1A, the pixel circuitry 100A includes a switch element 111A and a storage capacitor 112A. The switch element 111A is implemented by an N-type metal-oxide-semiconductor (NMOS) transistor having a gate coupled to a scan line SC for receiving a scan signal, a first source/drain coupled to a data line DA for receiving a pixel signal, and a second source/drain coupled to a pixel electrode Pix. The storage capacitor 112A is also implemented by an NMOS transistor having a gate coupled to the pixel electrode Pix and both of a first source/drain and a second source/drain coupled to a voltage, e.g. a voltage of a common electrode. When the scan signal is asserted to conduct the switch element 111A, the pixel signal on the data line DA is delivered to the pixel electrode Pix and then is stored within the storage capacitor 112A to control orientation of liquid crystal.
As known, the NMOS transistors are fabricated on a P-type substrate coupled to a negative power voltage VSSA. If a voltage range of the pixel signal is between a positive power voltage VDDA and the negative power voltage VSSA, not all pixel signals within such voltage range can be delivered to the pixel electrode Pix via the switch element 111 due to body effect. Namely, only pixel signals within a voltage range between the voltage VSSA and the voltage (VDDA−ΔV) can be delivered to the pixel electrode Pix, except those within a high-voltage range between the voltage (VDDA−ΔV) and the voltage VDDA. As a result, the voltage range passing though the switch element 111 is restricted.
In addition, the storage capacitor 112A is also called as an NMOS capacitor whose capacitance changes as a gate voltage under lower operation frequency. FIG. 1C is a curve of a capacitance of the MOS capacitor under lower operation frequency. Referring to FIG. 1C, a curves 101 shows the capacitance Cgb of the NMOS capacitor. When the gate voltage Vg is smaller than zero, an accumulation layer is formed between the gate and the substrate to serve as a capacitor. When the gate voltage Vg is larger than zero, but smaller than a threshold voltage Vtn, a depletion layer is formed in the substrate under a gate oxide, and the depth of the depletion layer is increased with the increase of the gate voltage Vg to reduce the capacitance Cgb of the NMOS capacitor. In the meanwhile, the capacitance Cgb of the NMOS capacitor is constructed of a gate capacitor and the depletion layer capacitor in series connection, wherein the gate capacitor is formed by two parallel plates of the gate and the depletion layer. In other words, under low operation frequency, the capacitance Cgb of the MOS capacitor is not as expected when the gate voltage Vg is larger than zero, but smaller than the threshold voltage Vtn. When the gate voltage Vg is larger than the threshold voltage Vtn, a channel layer is formed in the substrate under a gate oxide layer, and the capacitance Cgb of the NMOS capacitor is constructed of the gate capacitor formed by two parallel plates of the gate and the channel layer.
FIG. 1B is a circuit diagram of a conventional pixel circuitry. Referring to FIG. 1B, the switch element 111B and the storage capacitor 112B are implemented by PMOS transistors, wherein the PMOS transistors are fabricated on an N-type substrate coupled to the positive power voltage VDDA. Due to body effect, only pixel signals within a voltage range between the voltage (VSSA+ΔV) and the voltage VDDA can be delivered to the pixel electrode Pix, except those within a low-voltage range between the voltage VSSA and the voltage (VSSA+ΔV). As a result, the voltage range passing though the switch element 111B is restricted. Referring to FIG. 1C, a curve 102 shows the capacitance Cgb of the storage capacitor 112 implemented by PMOS transistor and called as PMOS capacitor. Similarly, the capacitance Cgb of the PMOS capacitor is not as expected under low operation frequency when the gate voltage is smaller than zero, but larger than a threshold voltage Vtp. There should be a circuit design in the pixel circuitry to solve the problems of voltage restriction and insufficient capacitance.